- Date Created
- 2024-08-30 08:46:40
- Last Updated
- 2024-08-30 08:46:40
- UUID
- 00f86610-96c6-4fb7-85f2-0de66a82f7ad
Title Update Infos: Introduction to Logic Circuits & Logic Design with Verilog
- Package Update Info
- Springer Nature - Springer Engineering eBooks 2019 English International
- Description
- The Date '4/10/2019' could not be parsed.
- Status
- Failed
- Type
- Changed Title
- Start Time
- 2024-08-30
- End Time
- 2024-08-30
- KBART Field
- access_start_date
- Old Value
- 2019-04-10
- New value
- 4/10/2019