Title Update Infos: Introduction to Logic Circuits & Logic Design with Verilog

Package Update Info
Springer Nature - Springer Engineering eBooks 2024 English International
Title
Introduction to Logic Circuits & Logic Design with Verilog
Description
New Title 'Introduction to Logic Circuits & Logic Design with Verilog'
Status
Successful
Type
New Title
Start Time
2024-01-31
End Time
2024-01-31
KBART Field
Empty
Old Value
Empty
New value
Empty
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Date Created
2024-01-31 06:37:46
Last Updated
2024-01-31 06:37:46
UUID
3f454ba4-a206-40cd-bde0-b11c1328a007


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