- Date Created
- 2024-01-31 06:37:45
- Last Updated
- 2024-01-31 06:37:45
- UUID
- 6da60d21-af1a-44b2-a50f-49ecd8accb9b
Title Update Infos: Introduction to Logic Circuits & Logic Design with VHDL
- Package Update Info
- Springer Nature - Springer Engineering eBooks 2024 English International
- Description
- New Title 'Introduction to Logic Circuits & Logic Design with VHDL'
- Status
- Successful
- Type
- New Title
- Start Time
- 2024-01-31
- End Time
- 2024-01-31
- KBART Field
- Empty
- Old Value
- Empty
- New value
- Empty